This invention relates generally to compound CMOS and bipolar transistor structures, and more particularly the invention relates to compound transistor structures which are operable at lower voltages while maintaining operating speed.
Disclosed in my U.S. Pat. No. 5,021,858 is a CMOS transistor structure which includes regions of opposite polarity within the drain region that act as minority carrier injectors. The drain region forms the base region, the injector region forms the emitter, and the semiconductor body region forms the collector of a bipolar transistor. The resulting structure has a much higher transconductance with no increase in input capacitance, resulting in an increase in operating speed.
In one embodiment of the structure, a CMOS transistor pair is fabricated in the surface of a lightly doped (on the order of 10.sup.12 atoms per cubic centimeter) semiconductor body such as an epitaxial layer formed on a supporting substrate. The drain region of each transistor is lightly doped (on the on the order of 10.sup.16 atoms per cubic centimeter) and a junction diode contact is made thereto adjacent to the drain contact. The resistivity of the drain region is sufficiently high to allow formation of an emitter electrode contact to the drain region by the more heavily doped region. The common gate terminals function as the device input, and the common injecting electrodes function as the device output.
In operation, the drains of the transistors are connected together and form the bases of bipolar transistors with the injecting diodes functioning as emitter followers. The diodes inject minority carriers when the MOS gates are turned on and cause a significant reduction in output resistance. The use of an auxiliary P-N junction injector in conjunction with one transistor pair when operated below 3 volts of a complimentary MOS transistor pair, while retaining the connection between the two drains, overcomes problems of slow switching speed observed in the application of the P-N junction minority carrier injector to a DMOS transistor.
The present invention is directed to a similar compound modulated integrated transistor structure which is operable at lower voltages.